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single channel, 128- /256 - position, i 2 c/spi, nonvolatile digital potentiometer data sheet AD5121 / ad5141 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. spec ifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o . box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2012 analog devices, inc. all rights reserved. technical support www.analog.com features 10 k and 100 k resistance options resistor tolerance : 8% maximum wiper current: 6 ma low temperature coefficient: 35 ppm/ c wide bandwidth: 3 mhz fast start - up time < 75 s linear gain setting mode single - and dual - supply operation independ ent logic supply : 1.8 v to 5.5 v wide operating temperature : ? 40 c to +125c 3 mm 3 mm lfcsp package 4 kv esd protection applications portable electronics level adjustment lcd panel brightness and contrast controls programmable filters, delays, and ti me constants programmable power supplies general description the AD5121 / ad5141 potentiometers provide a nonvolatile solution for 128 - /256 - position adjustment applicati ons , offering guaranteed low resistor tolerance errors of 8% and up to 6 ma current density in the a, b, and w pins. the low resistor tolerance and low nominal temperature coefficient simplify open - loop applications as well as applications requiring tole rance matching. the linear gain setting mode allows independent programming of the resistance between the digital potentiometer terminals, through r aw and r wb string resistors , allowing very accurate resistor matching. the high bandwidth and low total har monic distortion (thd) ensure optimal performance for ac signals, making it suitable for filter design. the low wiper resistance of only 40 ? at the ends of the resistor array allow s for pin - to - pin connection. the wiper values can be set through an spi - /i 2 c - compatible digital interface that is also used to read back the wiper register and ee prom content s. the AD5121 / ad5141 is available in a compact, 16 - lead, 3 mm 3 mm lfcsp . the parts are guaranteed to operate over the extended industrial temperature range of ? 40c to +125c. functional block di agram v dd inde p v ss gnd w p v logic 7/8 serial interface power-on reset rdac input register eeprom memory a w b AD5121/ ad5141 sync/addr0 sclk/sc l sdi/sd a sdo/addr1 dis reset 10940-001 figure 1. table 1 . family models model channel position interface package ad5123 1 quad 128 i 2 c lfcsp ad5124 quad 128 spi/i 2 c lfcsp ad5124 quad 128 spi tssop ad5143 1 quad 256 i 2 c lfcsp ad5144 quad 256 spi/i 2 c lfcsp ad5144 quad 256 spi tssop ad5144a quad 256 i 2 c tssop ad5122 dual 128 spi lfcsp/tssop ad5122a dual 128 i 2 c lfcsp/tssop ad5142 dual 256 spi lfcsp/tssop ad5142a dual 256 i 2 c lfcsp/tssop AD5121 single 128 spi/i 2 c lfcsp ad5141 single 256 spi/i 2 c lfcsp 1 two potentiometers and two rheostats. free datasheet http:///
AD5121/ad5141 data sheet rev. 0 | pa ge 2 of 32 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics AD5121 .......................................... 3 electrical characteristics ad5141 .......................................... 6 interface timing specifications .................................................. 9 shift register and timing diagrams ....................................... 10 absolute maximum ratings .......................................................... 12 thermal resistance .................................................................... 12 esd caution ................................................................................ 12 pin configuration and function descriptions ........................... 13 typical performance characteristics ........................................... 14 test circuits ..................................................................................... 19 theory of operation ...................................................................... 20 rdac register and eepro m .................................................. 20 input shift register .................................................................... 20 serial data digital interface selection, dis ............................ 20 spi serial data interface ............................................................ 20 i 2 c serial data interface ............................................................ 22 i 2 c address .................................................................................. 22 advanced control modes ......................................................... 23 eeprom or rdac register protection ................................. 24 load rdac input register ( l rdac ) ..................................... 24 indep pin ................................................................................... 24 rdac architecture .................................................................... 27 programming the va riable resistor ......................................... 27 programming the potentiometer divider ............................... 28 terminal voltage operating range ......................................... 29 power - up sequence ................................................................... 29 layout and power supply biasing ............................................ 29 outline dimensions ....................................................................... 30 ordering guide .......................................................................... 30 revision history 10/ 12 rev ision 0: initial version free datasheet http:///
data sheet AD5121/ad5141 rev. 0 | page 3 of 32 specifications electrical character istics AD5121 v dd = 2 .3 v to 5.5 v, v ss = 0 v; v dd = 2.25 v to 2.75 v, v ss = ?2.25 v to ?2.75 v; v logic = 1.8 v to 5.5 v, ?40c < t a < +125c, unless otherwise noted. table 2 . parameter symbol test conditions/comments min typ 1 max unit dc characteris tics rheostat mode (all rdacs) resolution n 7 bits resistor integral nonlinearity 2 r - inl r ab = 10 k ? v dd 2.7 v ? 1 0. 1 + 1 lsb v dd < 2.7 v ? 2.5 1 + 2.5 lsb r ab = 100 k ? v dd 2.7 v ? 0.5 0.1 + 0.5 lsb v dd < 2.7 v ? 1 0. 25 + 1 lsb resistor differential nonlinearity 2 r - dnl ? 0.5 0. 1 +0.5 lsb nominal resistor tolerance r ab /r ab ? 8 1 +8 % resistance temperature coefficient 3 (r ab /r ab )/t 10 6 code = full scale 35 ppm/c wip er resistance 3 r w code = zero scale r ab = 10 k ? 55 125 ? r ab = 100 k ? 130 400 ? bottom s cale or top scale r bs or r ts r ab = 10 k ? 40 80 ? r ab = 100 k ? 60 230 ? dc characteristics poten tiometer divider mode (all rdacs) integral nonlinearity 4 inl r ab = 10 k ? ? 0.5 0. 1 + 0.5 lsb r ab = 100 k ? ? 0. 25 0.1 +0. 25 lsb differential nonlinearity 4 dnl ? 0. 25 0. 1 +0. 25 lsb full - scale error v wfse r ab = 10 k ? ? 1 .5 ? 0.1 lsb r ab = 100 k ? ? 0.5 0. 1 + 0.5 lsb zero - scale error v wzse r ab = 10 k ? 1 1.5 lsb r ab = 100 k ? 0. 25 0.5 lsb voltage divider temperature coefficient 3 (v w /v w )/t 10 6 code = half scale 5 ppm/c free datasheet http:///
AD5121/ad5141 data sheet rev. 0 | pa ge 4 of 32 parameter symbol test conditions/comments min typ 1 max unit resistor terminals maximum continuous current i a , i b , and i w r ab = 10 k ? ? 6 +6 ma r ab = 100 k ? ? 1.5 +1.5 ma terminal voltage range 5 v ss v dd v capacitance a, capacitance b 3 c a , c b f = 1 mhz, measured to gnd , code = half scale r ab = 10 k ? 25 pf r ab = 100 k ? 12 pf capacitance w 3 c w f = 1 mhz, measured to gnd, code = half scale r ab = 10 k ? 12 pf r ab = 100 k ? 5 pf common - mode leakage current 3 v a = v w = v b ? 500 15 + 500 na digital inputs input logic 3 high v inh v log ic = 1.8 v to 2.3 v 0.8 v logic v v logic = 2.3 v to 5.5 v 0.7 v logic v low v inl 0.2 v logic v input hysteresis 3 v hyst 0.1 v logic v input current 3 i in 1 a input capacitance 3 c in 5 pf digital outputs output high voltage 3 v oh r pull - up = 2.2 k ? to v logic v logic v output low voltage 3 v ol i sink = 3 ma 0.4 v i sink = 6 ma , v logic > 2.3 v 0.6 v three - state leakage current ? 1 +1 a three - state output capacitance 2 pf power supplies single - supply power range v ss = gnd 2.3 5.5 v dual - supply power range 2.25 2.75 v logic supply range single s upply, v ss = gnd 1.8 v dd v dual s upply, v ss < gnd 2.25 v dd v positive supply current i dd v ih = v logic or v il = gnd v d d = 5.5 v 0.7 5.5 a v dd = 2.3 v 400 na negative supply current i ss v ih = v logic or v il = gnd ? 5.5 ? 0.7 a ee prom store current 3 , 6 i dd_ee prom _store v ih = v logic or v il = gnd 2 ma ee prom read current 3 , 7 i dd_ee prom _read v ih = v logic or v il = gnd 320 a logic supply current i logic v ih = v logic or v il = gnd 1 120 na power dissipation 8 p diss v ih = v logic or v il = gnd 3.5 w power supply rejection ratio psr r ? v dd / ? v ss = v dd 10%, code = full scale ? 66 ? 60 db free datasheet http:///
data sheet AD5121/ad5141 rev. 0 | page 5 of 32 parameter symbol test conditions/comments min typ 1 max unit dynamic characteristics 9 bandw idth bw ? 3 db r ab = 10 k ? 3 mhz r ab = 100 k ? 0.43 mhz total harmonic distortion thd v dd /v ss = 2.5 v, v a = 1 v rms, v b = 0 v, f = 1 khz r ab = 10 k ? ? 80 db r ab = 100 k ? ? 90 db resistor noise density e n_wb code = half scale, t a = 25c, f = 10 khz r ab = 10 k ? 7 nv/hz r ab = 100 k ? 20 nv/hz v w settling time t s v a = 5 v, v b = 0 v, from zero scale to full scale, 0.5 lsb error band r ab = 10 k ? 2 s r ab = 100 k ? 12 s endurance 10 t a = 25c 1 mcycles 100 kcycles data retention 11 50 years 1 typical values represent average readings at 25c, v dd = 5 v, v ss = 0 v, and v logic = 5 v . 2 resistor integral nonlinearity (r - inl) error is the deviation from an ideal value mea sured between the maximum resistance and the minimum resistance wiper positions. r - dnl measures the relative step change from ideal between successive tap positions. the maximum wiper current is limited to (0.7 v dd )/r ab . 3 guaranteed by design and charac terization, not subject to production test. 4 inl and dnl are measured at v wb with the rdac configured as a potentiometer divider similar to a voltage output dac. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic op erating conditions. 5 r esistor t erminal a, r esistor t erminal b, and r esistor t erminal w have no limitations on polarity with respect to each other. dual - supply operation enables ground referenced bipolar signal adjustment . 6 different from operating curren t; supply current for eeprom program lasts approximately 30 ms . 7 different from operating current; supply current for eeprom read lasts approximately 20 s . 8 p diss is calculated from (i dd v dd ) + (i logic v logic ). 9 all dynamic characteristics use v dd / v ss = 2.5 v, and v logic = 2. 5 v. 10 endurance is qualified to 100 ,000 cycles per jedec standard 22, method a117 and measured at ?40c to +125c . 11 retention lifetime equivalent at junction temperature (t j ) = 125c per jedec standard 22, method a117. retention lifetime , based on an activation ener gy of 1 ev , derates wit h junction temperature in the flash/ee memory. free datasheet http:///
AD5121/ad5141 data sheet rev. 0 | pa ge 6 of 32 electrical character istics ad5141 v dd = 2.3 v to 5.5 v, v ss = 0 v; v dd = 2.25 v to 2.75 v, v ss = ?2.25 v to ?2.75 v; v logic = 1.8 v to 5.5 v, ? 40c < t a < +125c, unless otherwise noted. table 3 . parameter symbol test conditions/comments min typ 1 max unit dc characteristics rheostat mode (all rdacs) resolution n 8 bits resistor integral nonlinearity 2 r - inl r a b = 10 k ? v dd 2.7 v ? 2 0.2 +2 lsb v dd < 2.7 v ? 5 1.5 +5 lsb r ab = 100 k ? v dd 2.7 v ? 1 0.1 +1 lsb v dd < 2.7 v ? 2 0.5 +2 lsb resistor differential nonlinearity 2 r - dnl ? 0.5 0.2 +0.5 lsb nominal resistor tolerance r ab /r ab ? 8 1 +8 % resistance temperature coefficient 3 (r ab /r ab )/t 10 6 code = full scale 35 ppm/c wiper resistance 3 r w code = zero scale r ab = 10 k ? 55 125 ? r ab = 100 k ? 130 400 ? bottom s cale or top scale r bs or r ts r ab = 10 k ? 40 80 ? r ab = 100 k ? 60 230 ? dc characteristics potentiometer divider mode (all rdacs) integral nonlinearity 4 inl r ab = 10 k ? ? 1 0.2 +1 lsb r ab = 100 k ? ? 0.5 0.1 +0.5 lsb differential nonlinearity 4 dnl ? 0.5 0.2 +0.5 lsb full - scale error v wfse r ab = 10 k ? ? 2.5 ? 0.1 lsb r ab = 100 k ? ? 1 0.2 +1 lsb zero - scale error v wzse r ab = 10 k ? 1. 2 3 lsb r ab = 100 k ? 0.5 1 lsb voltage divider temperature coefficient 3 (v w /v w )/t 10 6 code = half scale 5 ppm/c free datasheet http:///
data sheet AD5121/ad5141 rev. 0 | page 7 of 32 parameter symbol test conditions/comments min typ 1 max unit resistor terminals maximum continuous current i a , i b , and i w r ab = 1 0 k ? ? 6 +6 ma r ab = 100 k ? ? 1.5 +1.5 ma terminal voltage range 5 v ss v dd v capacitance a, capacitance b 3 c a , c b f = 1 mhz, measured to gnd , code = half scale r ab = 10 k ? 25 pf r ab = 100 k ? 12 pf capacitance w 3 c w f = 1 mhz, measured to gnd, code = half scale r ab = 10 k ? 12 pf r ab = 100 k ? 5 pf common - mode leakage current 3 v a = v w = v b ? 500 15 + 500 na digital inputs input logic 3 high v inh v logic = 1.8 v to 2.3 v 0.8 v logic v v logic = 2.3 v to 5.5 v 0.7 v logic v low v inl 0.2 v logic v input hysteresis 3 v hyst 0.1 v logic v input current 3 i in 1 a input capacitance 3 c in 5 pf digital outputs output high v oltage 3 v oh r pull - up = 2.2 k ? to v logic v logic v output low voltage 3 v ol i sink = 3 ma 0. 4 v i sink = 6 ma , v logic > 2.3v 0.6 v three - state leakage current ? 1 +1 a three - state output capacitance 2 pf power supplies single - supply power range v ss = gnd 2.3 5.5 v dual - supply power range 2.25 2.75 v logic supply range single s upply, v ss = gnd 1.8 v dd v dual s upply, v ss < gnd 2.25 v dd v positive supply current i dd v ih = v logic or v il = gnd v dd = 5.5 v 0.7 5.5 a v dd = 2.3 v 400 na negative supply current i ss v ih = v logic or v il = gnd ? 5.5 ? 0.7 a ee prom store current 3 , 6 i dd_ee prom _store v ih = v logic or v il = gnd 2 ma ee prom read current 3 , 7 i dd_ee prom _read v ih = v logic or v il = gnd 320 a logic supply current i logic v ih = v logic or v il = gnd 1 120 na power dissipation 8 p diss v ih = v logic or v il = gnd 3.5 w power supply rejection ratio psr ? v dd / ? v ss = v dd 10%, code = full scale ? 66 ? 60 db free datasheet http:///
AD5121/ad5141 data sheet rev. 0 | pa ge 8 of 32 parameter symbol test conditions/comments min typ 1 max unit dynamic characteristics 9 bandwi dth bw ? 3 db r ab = 10 k ? 3 mhz r ab = 100 k ? 0.43 mhz total harmonic distortion thd v dd /v ss = 2.5 v, v a = 1 v rms, v b = 0 v, f = 1 khz r ab = 10 k ? ? 80 db r ab = 100 k ? ? 90 db resistor noise density e n_wb code = half scale, t a = 25c, f = 10 khz r ab = 10 k ? 7 nv/hz r ab = 100 k ? 20 nv/hz v w settling time t s v a = 5 v, v b = 0 v, from zero scale to full scale, 0.5 lsb error band r ab = 10 k ? 2 s r ab = 100 k ? 12 s endurance 10 t a = 25c 1 mcycles 100 kcycles data retention 11 50 years 1 typical values represent average readings at 25c, v dd = 5 v, v ss = 0 v, and v logic = 5 v. 2 resistor integral nonlinearity error (r - inl) is the deviation from an ideal value measured between the maximum re sistance and the minimum resistance wiper positions. r - dnl measures the relative step change from ideal between successive tap positions. the maximum wiper current is limited to (0.7 v dd )/r ab . 3 guaranteed by design and characterization, not subject to production test. 4 inl and dnl are measured at v wb with the rdac configured as a potentiometer divider similar to a voltage output dac. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monoto nic operating conditions. 5 r esistor t erminal a, r esistor t erminal b, and r esistor t erminal w have no limitations on polarity with respect to each other. dual - supply operation enables ground referenced bipolar signal adjustment . 6 different from operating current; supply current for eeprom program lasts approximately 30 ms . 7 different from operating current; supply current for eeprom read lasts approximately 20 s . 8 p diss is calculated from (i dd v dd ) + (i logic v logic ). 9 all dynamic characteristics us e v dd / v ss = 2.5 v, and v logic = 2. 5 v. 10 endurance is qualified to 100,000 cycles p er jedec standard 22, method a117 and measured at ?40c to +125c . 11 retention lifetime equivalent at junction temperature (t j ) = 125c per jedec standard 22, method a117. retention lifetime , based on an activation ener gy of 1 ev , derates with junction te mperature in the flash/ee memory. free datasheet http:///
data sheet AD5121/ad5141 rev. 0 | page 9 of 32 interface timing specification s v logic = 1.8 v to 5.5 v; all specifications t min to t max , unless otherwise noted . table 4 . spi interface parameter 1 test conditions/c omments min typ max unit description t 1 v logic > 1.8 v 20 ns sclk cycle time v logic = 1.8 v 30 ns t 2 v logic > 1.8 v 10 ns sclk high time v logic = 1.8 v 15 ns t 3 v logic > 1.8 v 10 ns sclk low time v logic = 1.8 v 15 ns t 4 10 ns sync -to - sclk falling edge setup time t 5 5 ns data setup time t 6 5 ns data hold time t 7 10 ns sync rising edge to next sclk fall ignored t 8 2 20 ns minimum sync high time t 9 3 50 ns sclk rising edge to sdo valid t 10 500 ns sync rising edge to sdo pin disable 1 all input signals are specified with t r = t f = 1 ns/v (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. 2 refer to t eeprom_program and t eeprom_readback for memory commands operations (see table 6 ) . 3 r pull_up = 2.2 k ? to v dd with a capacitance load of 168 pf. table 5 . i 2 c interface parameter 1 test conditions/comments min typ max unit description f scl 2 standard mode 100 khz serial clock frequency fast mode 400 khz t 1 standard mode 4.0 s scl high time , t high fast mode 0.6 s t 2 standard mode 4.7 s scl low time , t low fast mode 1.3 s t 3 standard mode 250 ns d ata setup ti me , t su; dat fast mode 100 ns t 4 standard mode 0 3.45 s d ata hold time , t hd; dat fast mode 0 0.9 s t 5 standard mode 4.7 s s etup time for a repeated start condition , t su; sta fast mode 0.6 s t 6 standard mode 4 s h old time (repeated) for a start condition , t hd; sta fast mode 0.6 s t 7 standard mode 4.7 s b us free time between a stop and a start condition , t buf fast mode 1.3 s t 8 standard mode 4 s s etup time for a stop condition , t su; sto fast mode 0.6 s t 9 standard mode 1000 ns r ise time of sda signal , t rda fast mode 20 + 0.1 c l 300 ns t 10 standard mode 300 ns f all time of sda signal , t fda fast mode 20 + 0.1 c l 300 ns t 11 standard mode 1000 ns r ise time of scl signal , t rcl fast mode 20 + 0.1 c l 300 ns t 11a standard mode 1000 ns r ise time of scl signal after a repeated start condition and after an acknowledge bit , t rcl1 (not shown in figure 3 ) fast mode 20 + 0.1 c l 300 ns free datasheet http:///
AD5121/ad5141 data sheet rev. 0 | pa ge 10 of 32 parameter 1 test conditions/comments min typ max unit description t 12 standard mode 300 ns f all time of scl signal , t fcl fast mode 20 + 0.1 c l 300 ns t sp 3 fast mode 0 50 ns pulse width of suppressed spike (not shown in figur e 3 ) 1 maximum bus capacitance is limited to 400 pf. 2 the sda and scl timing is measured with the input filters enabled. switching off the input filters improves the transfer rate ; however, it has a negative effect on the emc behavior of the part. 3 input filtering on the scl and sda inputs suppresses noise spikes that are less than 50 ns for fast mode. table 6 . control pins parameter min typ max unit description t 1 1 s end command to lrdac falling edge t 2 50 ns minimum lrdac low time t 3 0.1 10 s reset low time t eeprom_program 1 15 50 ms memory program time (not shown in figure 6 ) t eeprom_readback 7 30 s memory readback time (not shown in figure 6 ) t power_up 2 75 s power - on eeprom resto re time (not shown in figure 6 ) t reset 30 s reset eeprom restore time (not shown in figure 6 ) 1 ee prom program time depends on the temperature and ee prom write cycles. higher timing is expected at lower temp erature s and higher write cycles. 2 maximum time after v dd ? v ss is equal to 2.3 v. shi f t r egister and timing d iagrams data bits db8 db15 (msb) db0 (lsb) d7 d6 d5 d4 d3 d2 d1 d0 address bits a0 a1 a2 c2 c1 c0 a3 c3 control bits db7 10940-004 figure 2. input shift re gister content s t 7 t 6 t 2 t 4 t 11 t 12 t 6 t 5 t 10 t 1 scl sda p s s p t 3 t 8 t 9 10940-005 figure 3. i 2 c serial interface timing diagram (typical write sequence) c3 t 4 t 2 t 3 t 5 t 6 c2 c1 c0 d7 d6 d5 d2 d1 d0 sdi *previous command received. sclk sync c3* sdo c2* c1* c0* d7* d6* d5* d2* d1* d0* t 8 t 9 t 10 t 7 t 1 10940-006 figure 4. spi serial interface timing diagram, cpol = 0, cpha = 1 free datasheet http:///
data sheet AD5121/ad5141 rev. 0 | page 11 of 32 c3 t 4 t 2 t 3 t 5 t 6 c2 c1 c0 d7 d6 d5 d2 d1 d0 sdi *previous command received. sclk sync c3* sdo c2* c1* c0* d7* d6* d5* d2* d1* d0* t 8 t 9 t 10 t 7 t 1 10940-007 figure 5. spi serial interface timing diagram, cpol = 1, cpha = 0 spi interface i 2 c interface scl sclk sync sda lrdac reset p t 1 t 2 t 3 10940-008 figure 6 . control pins timing diagram free datasheet http:///
AD5121/ad5141 data sheet rev. 0 | pa ge 12 of 32 absolute maximum rat ings t a = 25c, unless otherwise noted. table 7 . parameter rating v dd to gnd ? 0.3 v to +7.0 v v ss to gnd + 0.3 v to ? 7.0 v v dd to v ss 7 v v logic to gnd ? 0.3 v to v dd + 0.3 v or +7.0 v (whichever is less) v a , v w , v b to gnd v ss ? 0.3 v, v dd + 0.3 v or +7.0 v (whichever is less) i a , i w , i b pulsed 1 frequency > 10 khz r aw = 10 k? 6 ma/d 2 r aw = 100 k? 1.5 ma/d 2 frequency 10 khz r aw = 10 k? 6 ma/d 2 r aw = 100 k? 1.5 ma/d 2 digital inputs ? 0.3 v to v lo gic + 0.3 v or +7 v (whichever is less) operating temperature range, t a 3 ? 40 c to +125c maximum junction temperature, t j m ax imum 150c storage temperature range ? 65c to +150c reflow soldering peak temperature 260c time at peak temperature 20 s ec to 40 sec package power dissipation (t j max ? t a )/ ja 1 maximum terminal current is bounded by the maximum current handling of the switch es, maximum power dissipation of the package, and maximum applied voltage across any two of the a, b, and w terminals at a given resistance. 2 d = p ulse duty factor. 3 includes programming of eeprom memory. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditio ns above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is defined by the jedec jesd51 standard, and the value is dependent on the test board and test environment. table 8 . thermal resistance package type ja jc unit 16- lead lfcsp 89.5 1 3 c/w 1 jedec 2s2p t est board, still air (0 m/sec air flow). esd caution free datasheet http:///
data sheet AD5121/ad5141 rev. 0 | page 13 of 32 pin configuration and fu nction descriptions pin 1 indic a t or 1 gnd 2 a 3 w 4 b v dd v ss 1 1 v logic sclk/sc l notes 1. internally connect the exposed pad to v ss . 12 sdi/sd a 10 9 5 6 7 8 dis 14 sdo/addr1 16 inde p 15 lrdac w p 13 AD5121/ ad5141 t o p view (not to scale) reset sync/addr0 10940-009 figure 7 . pin configuration table 9 . pin function descriptions pin no. mnemonic description 1 gnd ground pin, logic ground reference. 2 a terminal a of rdac . v ss v a v dd . 3 w wiper terminal of rdac. v ss v w v dd . 4 b terminal b of rdac . v ss v b v dd . 5 v ss negative power supply. decouple t his pin with 0.1 f ceramic capacitors and 10 f capacitors . 6 sync /addr0 programmable a ddress (add r 0 ) for multiple package decoding , dis = 1. synchronization data input, active low. when sync returns high, data is loaded into the rdac register, dis = 0. 7 reset hardware reset pin. refresh the rdac register s from ee prom . reset is activated at logic lo w . i f this pin is not used , t ie reset to v logic . 8 dis digital interface select (spi/i 2 c select). spi when dis = 0 (gnd) , i 2 c when dis = 1 (v logic ) . this pin cannot be left floatin g. 9 v dd positive power supply. decouple t his pin with 0.1 f ceramic capacitors and 10 f capacitors . 10 v logic logic power supply; 1.8 v to v dd . decouple t his pin with 0.1 f ceramic capacitors and 10 f capacitors . 11 sclk/scl spi serial clock line (s clk) . data is clocked in at logic low transition . i 2 c serial clock line (scl) . data is clocked in at logic low transition . 12 sdi/sda serial data input/output (sda), when dis = 1. serial data input (sdi), when dis = 0. 13 wp optio nal write protect. this pin prevents any changes to the present rdac and ee prom contents, except when reload ing the content of the ee prom into the rdac register. wp is activated at logic low. if this pin is not used, t ie wp to v logic 14 sdo/addr1 programmable address (addr 1 ) for multiple package decoding, when dis = 1. serial data output (sdo). this is an o pen - drain output pin, and it needs an external pull- up resistor when dis = 0. 15 indep linear gain setting mod e at power - up. each string resistor is loaded from its associate memory location. if indep is enabled, it cannot be disabled by the software . 16 lrdac load rdac. transfers the contents of the input register to the rdac register. this all ows asynchronous rdac update . lrdac is activated low . i f this pin is not used , t ie lrdac to v logi c . epad internally c onnect the exposed p ad to v ss . free datasheet http:///
AD5121/ad5141 data sheet rev. 0 | pa ge 14 of 32 typical performance characteristics ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0 100 200 r-inl (lsb) code (decimal) 10k ?, +125c 10k ?, +25c 10k ?, ?40c 100k ?, +125c 100k ?, +25c 100k ?, ?40c 10940-012 figure 8. r - inl vs. code ( ad5141 ) r-inl (lsb) code (decimal) ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 0 50 100 10k ?, +125c 10k ?, +25c 10k ?, ?40c 100k ?, +125c 100k ?, +25c 100k ?, ?40c 10940-013 figure 9. r - inl vs. code ( AD5121 ) 0 100 200 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 in l (lsb) code (decimal) 10k ?, ?4 0 c 10k ?, + 2 5 c 10k ?, + 12 5 c 100k ?, ?4 0 c 100k ?, + 2 5 c 100k ?, + 12 5 c 10940-014 figure 10 . inl vs. code ( ad5141 ) ?0.6 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0 100 200 r-dn l (lsb) code (decimal) 10k ?, +125c 10k ?, +25c 10k ?, ?40c 100k ?, +125c 100k ?, +25c 100k ?, ?40c 10940-015 figure 11 . r - dnl vs. code ( ad5141 ) code (decimal) ?0.30 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0 50 100 r-dn l (lsb) 10k ?, +125c 10k ?, +25c 10k ?, ?40c 100k ?, +125c 100k ?, +25c 100k ?, ?40c 10940-016 figure 12 . r - dnl vs. code ( AD5121 ) ?0.30 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 dn l (lsb) code (decimal) 10k ?, ?4 0 c 10k ?, +2 5 c 10k ?, +12 5 c 100k ?, ?4 0 c 100k ?, +2 5 c 100k ?, +12 5 c 10940-017 0 100 200 figure 13 . dnl vs. code ( ad5141 ) free datasheet http:///
data sheet AD5121/ad5141 rev. 0 | page 15 of 32 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0 50 100 in l (lsb) code (decimal) 10k ?, ?4 0 c 10k ?, + 2 5 c 10k ?, + 12 5 c 100k ?, ?4 0 c 100k ?, + 2 5 c 100k ?, + 12 5 c 10940-018 figure 14 . inl vs. code ( AD5121 ) ?50 0 50 100 150 200 250 300 350 400 450 potentiometer mode temperature coefficient (ppm/c) code (decimal) 100k ? 10k ? 10940-019 0 5 0 10 0 15 0 20 0 25 5 0 2 5 5 0 7 5 10 0 12 7 ad 512 1 ad 514 1 figure 15 . pot entiometer mode temp erature c o efficient (( v w /v w )/ t 10 6 ) vs. code 10940-020 0 10 0 20 0 30 0 40 0 50 0 60 0 70 0 80 0 ?4 0 1 0 6 0 1 25 1 10 curr e n t ( n a ) t empera t ur e ( c ) i dd , v dd = 2 . 3 v i dd , v dd = 3 . 3 v i dd , v dd = 5 v i logic , v logic = 2 . 3 v i logic , v logic = 3 . 3 v i logic , v logic = 5 v v d d = v l ogi c v s s = g n d figure 16 . supply current vs. temperature ?0.14 ?0.12 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0 50 100 dn l (lsb) code (decimal) 10k ?, ?4 0 c 10k ?, +2 5 c 10k ?, +12 5 c 100k ?, ?4 0 c 100k ?, +2 5 c 100k ?, +12 5 c 10940-021 figure 17 . dnl vs. code ( AD5121 ) 10940-122 ?50 0 50 100 150 200 250 300 350 400 450 rh e o s t a t m o d e t empe ra t ur e c o e ff i c i e n t ( pp m / c ) 10k? 100k? code (decimal) 0 5 0 10 0 15 0 20 0 25 5 0 2 5 5 0 7 5 10 0 12 7 ad 512 2 ad 514 2 figure 18 . rheosta t mode temperature coefficient (( r wb /r wb )/ t 10 6 ) vs. code 10940-023 0 20 0 40 0 60 0 80 0 100 0 120 0 0 1 2 3 4 5 i l ogi c curr e n t ( a ) i n pu t vo lt a g e (v) i 2 c , v logic = 1 . 8 v i 2 c , v logic = 2 . 3 v i 2 c , v logic = 3 . 3 v i 2 c , v logic = 5 v i 2 c , v logic = 5 . 5 v spi, v logic = 1 . 8 v spi, v logic = 2 . 3 v spi, v logic = 3 . 3 v spi, v logic = 5 v spi, v logic = 5 . 5 v figure 19 . i logic current vs. digital input voltage free datasheet http:///
AD5121/ad5141 data sheet rev. 0 | pa ge 16 of 32 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 0 1 0 10 0 1 k 10 k 100 k 1 m 10 m g a i n ( d b ) f r e q u e n c y ( h z) ad 51 21/ ad 514 1 0x80 ( 0x40 ) 0x40 ( 0x20 ) 0x20 ( 0x10 ) 0x10 ( 0x08 ) 0x8 ( 0x04 ) 0x4 ( 0x02 ) 0x2 ( 0x01 ) 0x1 ( 0x00 ) 0x0 0 10940-022 figure 20 . 10 k? gain vs. frequency vs. code 10940-025 ?10 0 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 2 0 20 0 2 k 20k 200 k t hd + n (d b ) f r e q u e n c y ( h z) 10 k ? 100 k ? v d d / v s s = 2 . 5 v v a = 1 v rm s v b = g n d c o d e = ha lf s ca l e n oi se f i lt e r = 22k h z figure 21 . total harmonic distortion plus noise (thd + n) vs. frequency ?100 ?80 ?60 ?40 ?20 0 20 10 100 1k 10k 100k 1m 10m phase (degrees) frequenc y (hz) quarter scale midscale full-scale v dd /v ss = 2.5v r ab = 10k 10940-026 figure 22 . normalized phase flatness vs. frequency, r ab = 10 k? ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 g a i n ( d b ) f r eq u en c y (h z) 1 0 10 0 1 k 10 k 100 k 1 m 10 m 0x80 (0x40 ) 0x40 (0x20 ) 0x20 (0x10 ) 0x10 (0x08 ) 0x8 (0x04 ) 0x4 (0x02 ) 0x2 (0x01 ) 0x1 (0x00 ) 0x0 0 ad 51 21 / ad 514 1 10940-123 figure 23 . 100 k? gain vs. frequency vs. code 10 k ? 100 k ? ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 0 0 . 00 1 0 . 0 1 0 . 1 1 t hd + n (d b ) vo l t a g e (v rms ) v dd /v ss = 2 . 5 v f i n = 1k h z c o d e = ha lf s ca l e n oi se f i lt e r = 2 2 k h z 10940-028 figure 24 . total harmonic distortion plus noise (thd + n) vs. amplitude ?80 ?90 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 10 100 1k 10k 100k 1m phase (degrees) frequenc y (hz) quarter scale midscale full-scale v dd /v ss = 2.5v r ab = 100k 10940-029 figure 25 . normalized phase flatness vs. frequency, r ab = 100 k? free datasheet http:///
data sheet AD5121/ad5141 rev. 0 | page 17 of 32 0 100 200 300 400 500 600 0 1 2 3 4 5 wiper on resis t ance ( ) volt age (v) 100k, v dd = 2.3v 100k, v dd = 2.7v 100k, v dd = 3v 100k, v dd = 3.6v 100k, v dd = 5v 100k, v dd = 5.5v 10k, v dd = 2.3v 10k, v dd = 2.7v 10k, v dd = 3v 10k, v dd = 3.6v 10k, v dd = 5v 10k, v dd = 5.5v 10940-030 figure 26 . incremental wiper on resistanc e vs. v dd 0 1 2 3 4 5 6 7 8 9 10 0 20 40 60 80 100 120 0 10 20 30 40 50 60 bandwidth (mhz) code (decimal) ad5141 AD5121 10k ? + 0pf 10k ? + 75pf 10k ? + 150pf 10k ? + 250pf 100k ? + 0pf 100k ? + 75pf 100k ? + 150pf 100k ? + 250pf 10940-031 figure 27 . maximum bandwidth vs. code vs. net capacitance ?0 . 1 0 0 . 1 0 . 2 0 . 3 0 . 4 0 . 5 0 . 6 0 . 7 0 . 8 0 5 1 0 1 5 r el a t i ve vo l t a g e (v) t i me ( s ) 0x80 t o 0x7 f , 100k 0x80 t o 0x7 f , 10k v d d / v s s = 2 . 5 v v a = v d d v b = v s s 10940-032 figure 28 . maximum transition glitch 0 0 . 2 0 . 4 0 . 6 0 . 8 1 . 0 1 . 2 0 0 . 0 0 0 5 0 . 0 0 1 0 0 . 0 0 1 5 0 . 0 0 2 0 0 . 0 0 2 5 ?4 0 0 ?5 0 0 ?6 0 0 ?3 0 0 ?2 0 0 ?1 0 0 0 1 0 0 2 0 0 3 0 0 4 0 0 5 0 0 6 0 0 resistor drift (ppm) cumulative probability probability density 10940-033 figure 29 . resistor life t ime drift ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 100 1k 10k 100k 1m 10m psrr (db) frequenc y (hz) 10k 100k 10940-034 figure 30 . power supply rejection ratio (psrr) vs. frequency ?0.020 ?0.015 ?0.010 ?0.005 0 0.005 0.010 0.015 0.020 0 500 1000 1500 2000 rel a tive vo lt age (v) time (ns) 10940-035 figure 31 . digital feedthrough free datasheet http:///
AD5121/ad5141 data sheet rev. 0 | pa ge 18 of 32 ?120 ?100 ?80 ?60 ?40 ?20 0 10 100 1k 10k 100k 1m 10m gain (db) frequenc y (hz) 10k 100k 10940-036 shutdown mode enabled figure 32 . shutdown isolation vs. frequency 0 1 2 3 4 5 6 7 0 50 100 150 200 250 0 25 50 75 100 125 AD5121 theoretica l i max (ma) ad5141 100k? 10k? code (decimal) 10940-037 figure 33 . theoreti cal maximum current vs. code free datasheet http:///
data sheet AD5121/ad5141 rev. 0 | page 19 of 32 test circuits figure 34 to figure 38 define the test conditions used in the specifications section. a w b nc i w dut v ms nc = no connect 10940-038 figure 34 . re sistor integral nonlinearity error (rheostat operation; r - inl, r - dnl) a w b dut v ms v+ v+ = v dd 1lsb = v+/2 n 10940-039 figure 35 . potentiometer divider nonlinearity error (inl, dnl) 10940-040 a w n c b du t i w = v d d / r n o m i n a l v m s 1 v w r w = v m s 1 / i w nc = n o c o nn e c t figure 36 . wiper resistance a w b v ms v+ = v dd 10% psrr (db) = 20 log v ms v dd ( ) ~ v a v dd v ms % v dd % pss ( %/% ) = v+ 10940-041 figure 37 . power supply sensitivity and power supply rejection ratio (pss and psrr) + ? dut code = 0x00 0.1v v ss t o v dd r sw = 0.1v i sw i sw w b a = nc 10940-045 figure 38 . incremental o n resistance free datasheet http:///
AD5121/ad5141 data sheet rev. 0 | pa ge 20 of 32 theory of operation the AD5121 / ad5141 digital programmable potentiometers are designed to operate as true variable resistor s for analog signals within the terminal voltage range of v ss < v term < v dd . the resistor wiper position is determined by the rdac register contents. the rdac register acts as a scratchpad register that allows unlimited changes of resistance settings . a secondary register (the input register ) can be used to preload the rdac register data. the rdac register can be programmed with any position setting us ing the i 2 c or spi interface (depending on the model). when a desirable wiper position is found, this value can be stored in the eeprom memory. thereafter, the wiper position is always restored to that position for subsequent power - up s . the storing of eepr om data takes approximately 18 ms; during this time, the device is locked and does not acknowledge any new command , preventing any changes from taking place. rdac r egister and eeprom the rdac register directly controls the position of the digital potentiom eter wiper. for example, when the rdac register is loaded with 0x80 ( ad5141 , 256 taps) , the wiper is connected to half scale of the variable resistor. the rdac register is a standard logic register; there is no r estriction on the number of changes allowed . it is possible to both write to and read from the rdac register using the digital interface ( see ta ble 16) . the contents of the rdac register can be stored to the eeprom using c ommand 9 ( see table 16 ) . thereafter , the rdac register always set s at that position for any future on - off - on power supply sequence. it is possible to read back data saved into the eeprom with c ommand 3 ( see ta ble 16) . alternatively, the eeprom can be writ t e n to independently using c ommand 1 ( see ta ble 16) . input shift register for the AD5121 / ad5141 , the input shift register is 16 bits wide, as shown in figure 2 . the 16 - bit word consists of four control bits, followed by four address bits and by eight data bits i f the AD5121 rdac or ee prom registers are read from or written to the lowe st data bit (bit 0) is ignored. data is loaded msb first (bit 15). the four control bits determine the function of the software command , as listed in ta ble 11 and ta ble 16. serial data d igital interface s election , dis the AD5121 / ad5141 lfscp provide s the flexibility of a selectable interface. when the digital interface select (dis) pin is tied low, the spi mode is engaged. when the dis pin is tied high, the i 2 c mode is engaged. spi serial data interface the AD5121 / ad5141 contain a 4 - wire , spi - compatible digital interface (sdi, sync , sdo , and s clk). the write sequence begins by bringing the sync line low. the sync pin must be held low until the complete data - word is loaded from the sdi pin . data is loaded in at the s clk falling edge transition, as shown in figure 4 . when sync returns high, the serial dat a - word is decoded according to the instructions in ta ble 16. the AD5121 / ad5141 do not require a continuous sclk when sync is high. to minimize power consumption in the digital input buffers when the part is enable d , operate all serial interface pins close to the v logic supply rails. s ync interruption in a standalone write sequence for the AD5121 / ad5141 , the sync line is kept low for 16 falling edges of sclk, and the instruction is decoded when s ync is pulled high. however, i f the s ync line is kept low for less than 16 falling edges of sclk, the input shift register content is ignored , and the write sequence is considered invalid. sdo p in the serial data output pin (sdo) serves two purposes : to read back the contents of the control , ee prom , rdac , and input registers using command 3 (see table 11 and table 16 ), and to connect the a d5121 / ad5141 to daisy - chain mode. the sdo pin contains an internal open - drain output that needs an external pull - up resistor. th e sdo pin is enabled when sync is pulled low , and t he d ata i s clocked out of sdo on the rising edge of sclk. free datasheet http:///
data sheet AD5121/ad5141 rev. 0 | page 21 of 32 daisy - chain connection d aisy chaining minimizes the number of port pins required from the control ling ic. as shown in figure 39, the sdo pin of one package must be tie d to the sdi pin of the next package. the clock period may need to be increase d because the p ropagation delay of the line between subsequent devices. when two AD5121 / ad5141 devices are daisy chained, 32 bits of data are required. the first 16 bits assigned to u2, and the second 16 bits assigned to u1 , as shown in figure 40 . keep the sync pin low until all 32 b its are clocked into their respective serial registers. the sync pin is then pulled high to complete the operation. a t ypical connection is show n in figure 39 . to prevent data from mislocking ( for example, due to noise) the part includes an internal counter, if the clock falling edges count is not a multiple of 8, the part ignores the command . a valid clock count is 16, 24, or 32. the counter resets when sync returns high . mosi ss sclk miso microcontroller sdi sdo sclk sclk r p 2.2k ? r p 2.2k ? sdi sdo u1 u2 AD5121/ ad5141 AD5121/ ad5141 sync sync dais y -chain v logic v logic 10940-046 figure 39 . daisy - chain configuration db15 sclk sync mosi 1 2 16 db0 db15 sdo_u1 32 db15 db0 db15 db0 17 18 db0 input word for u2 input word for u1 input word for u2 undefined 10940-047 figure 40 . daisy - chain diagram free datasheet http:///
AD5121/ad5141 data sheet rev. 0 | pa ge 22 of 32 i 2 c serial data interf ace the ad5141 ha s 2 - wire , i 2 c - compatible serial interface . the se devices can be connected to an i 2 c bus as a slave device, under the control of a master device . see figure 3 f or a timing diagram of a typical write seq uence. the ad5141 support s standard (100 k hz) and fast (400 khz) data transfer modes. support is not provided for 10 - bit addressing and general call addressing. the 2 - wire serial bus protocol operates as follows: 1. the master initiates a data tr ansfer by establishing a start condition, which is when a high - to - low transition on the sda line occurs while scl is high. the following byte is the address byte, which consists of the 7 - bit slave address and a n r/ w bit. the slave device corresponding to the transmitted address responds by pu lling sda low during the ninth cl ock pulse (this is call ed the acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to, or read from, its shift register. if the r/ w bit is set high, the master reads from the slave device. however, if the r/ w bit is set low, the master writes to the slave device. 2. data is transmitted over the s erial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl. 3. when all data bits hav e been read from or written to , a stop condition is established. in write mode, the master p ulls the sda line high during the ten th clock pulse to establish a stop condition. in read mode, the master issues a no a cknowledge for the ninth clock pulse (that is, the sda line remains high). the master then brings the sda line low before the ten th clo ck pulse, and then high again during the ten th clock pulse to establish a stop condition. i 2 c address the ad5141 has two different pin address options available , as shown in table 10. table 10 . 24- lead lfcsp device address selection addr0 pin addr1 pin 7 - bit i 2 c device address v dd v dd 0100000 no connect 1 v dd 0100010 gnd v dd 0100011 v dd no connect 1 0101000 no connect 1 no connect 1 0101010 gnd n o connect 1 0101011 v dd gnd 0101100 no connect 1 gnd 0101110 gnd gnd 0101111 1 n ot available in bipolar mode ( v ss < 0 v ) or in low voltage mode ( v logic = 1.8 v ) . ta ble 11. simple command operation truth table command number co ntrol bits [db15:db12] address bits [db11:db8] 1 data bits [db7:db0] 1 c3 c2 c1 c0 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 operation 0 0 0 0 0 x x x x x x x x x x x x nop: do nothing 1 0 0 0 1 0 0 0 0 d7 d6 d5 d4 d3 d2 d1 d0 write contents of serial register d ata to rdac 2 0 0 1 0 0 0 0 0 d7 d6 d5 d4 d3 d2 d1 d0 write contents of serial register data to input register 3 0 0 1 1 x 0 0 0 x x x x x x d1 d0 read back contents d1 d0 data 0 1 eeprom 1 1 rdac 9 0 1 1 1 x x 0 0 x x x x x x x 1 copy rdac register to eeprom 10 0 1 1 1 x x 0 0 x x x x x x x 0 copy eeprom into rdac 14 1 0 1 1 x x x x x x x x x x x x software reset 15 1 1 0 0 0 0 0 0 x x x x x x x d0 software shutdown d0 conditio n 0 normal mode 1 shutdown mode 1 x = dont care. free datasheet http:///
data sheet AD5121/ad5141 rev. 0 | page 23 of 32 advanced control mod es the AD5121 / ad5141 digital potentiometers include a set of user programming features to address the wide number of applications for these universal adjustment devices ( see table 16 and table 18 ) . key programming features i nclude the following: ? input register ? linear gain setting mode ? low wiper resistance feature ? linea r i ncre ment and decrement instructions ? 6 db increment and decrement instructions ? burst m ode (i 2 c only) ? reset ? shutdown mode input r egister the AD5121 / ad5141 include one input register per rdac register. th is register allow s preload ing of the value for the associate d rdac register. this feature allows a synchronous and asynchr onous update of one or all the rdac registers at the same time. th ese register s can be written to using c ommand 2 and read back from using c ommand 3 (see ta ble 16) . the transfer from the input register to the rdac register is done asynchronously by the lrdac pin or synchronously by c ommand 8 (see ta ble 16) . if new data is loaded in a n rdac register , th is rdac register automatically overwrite s the associate d input register. linear gain setting mode the patented architecture of the AD5121 / ad5141 allows the independent control of each string resistor, r aw and r w b . to enable this feature , use command 16 (see ta ble 16 ) to set b it d2 of the control register ( see table 18 ) . this mode of operation can control the potentiometer as two independent rheostats connect ed at a single point, w terminal, as opposed to potentiometer mode where each resistor is complementary, r aw = r ab ? r wb . this feature enables a second input and a n rdac register per channel, as shown in table 16 ; however, the actual rdac content s remain unchanged. the same operations are valid for potentiometer and linear gain setting mode s. if the indep pin is pulled high, the device powers up in l inear gain setting mode and loads the values stored in the associat ed memory locations for each channel (see table 17 ). the indep pin and d2 bit are connected internally to a logic or gate, if any or both are 1, the part s cannot operate in potentiometer mode. low wiper resistanc e f eature the AD5121 / ad5141 include two commands to reduce the wiper resistance between the terminals when they achieve full scale or zero scale. these ext ra positions are called bottom scale, bs, and top scale, ts. the resistance between t erminal a and t erminal w at top scale is specified as r ts . s imilar ly , the bottom scale re s i stance between t erminal b and te rm i na l w is specifi ed as r bs . the contents of the rdac regist ers are unchanged by entering in these position s. there are two ways to exit f r o m top scale and bottom scale : by using c ommand 12 or command 13 (see ta ble 16) ; or by loading new data in a n rdac register, which includes increment/d ecrement operations and a shutdown command. table 12 and table 13 show the truth tables for the top scale position and the bottom scale position , respectively, when linear gain setting mod e is enable d . table 12. top scale truth table linear gain setting mode potentiometer mode r aw r wb r aw r wb r ab r ab r ts r ab table 13. bottom scale truth table linear gain setting mode potentiometer mode r aw r wb r aw r wb r ts r bs r ab r bs linear increment and decrement instructions the increment and decre ment commands ( command 4 and command 5 in ta ble 16 ) are useful for linear step adjustment applications. these commands simplify mi crocontroller software coding by allowing the controller to send an increment or decrement command to the device. the adjustment can be individual or in a ganged potentiometer arrangement , where all wiper positions are changed at the same time. for an incr ement command, executing command 4 automatically moves the wiper to the next resistance segment position . this command can be executed in a single channel or multiple channels . 6 db increment and decrement instructions two programming instructions produc e logarithmic taper increment or decrement of the wiper position control by an individual potentiometer or by a ganged potentiometer arrangement where all rdac register positions are changed simultaneously . the +6 db increment is activated by command 6, an d the ? 6 db decrement is activated by command 7 ( see table 16 ) . for example, starting with the zero - scale position and executing command 6 ten times moves the wiper in 6 db steps to the full - scale position . when the wipe r position is near the maximum setting, the last 6 db increment instruction cause s the wiper to go to the full - scale position ( see table 14) . free datasheet http:///
AD5121/ad5141 data sheet rev. 0 | pa ge 24 of 32 incr ementing the wiper position by + 6 db essentially doubles the rdac register value, whereas decrementing the wiper position by ? 6 db halves the register content. internally, the AD5121 / ad5141 use shift registers to shift the bits left and right to achieve a 6 db increment or decrement. these f unctions are useful for various audio/video level adjustments, especially for white led brightness settings in which human visual responses are more sensitive to large adjustments than to small adjustments. table 14 . detailed left shift and right shift functions for the 6 db step increment and decrement left shift (+6 db/step) right shift ( ? 6 db/step) 0000 0000 1111 1111 0000 0001 0111 1111 0000 0010 0011 1111 0000 0100 0001 1111 0000 1000 0000 1111 0001 0000 0000 0111 0010 0000 0000 0011 0100 0000 0000 0001 1000 0000 0000 0000 1111 1111 0000 0000 burst mode (i 2 c only) by enabli ng th e burst mode, multiple data bytes can be sent to the part consecutively. after the command byte, the part interprets the consecutive bytes as data bytes for the first command. a new command can be sent by generating a repeat start or by a stop and sta rt condition. th e burst mode is activ ated by setting bit d3 of the control register (see table 18 ), and if a reset or power - down is performed , it automatically resets. reset the AD5121 / ad5141 can be reset through software by executing command 1 4 (see table 16 ) o r through hardware on the low pulse of the reset pin. the re set command loads the rdac register with the contents of the eeprom and takes approximately 30 s. the eeprom is preloaded to midscale at the factory, and initial power - up is, accordingly, at midscale. ti e reset to v dd if the reset pin is not used. shutdown mode the AD5121 / ad5141 can be placed in shutdown mode by executing the software shutdown command, command 15 (see ta ble 16) ; and by setting the lsb (d0) to 1. this feature places the rdac in a special state. the contents of the rdac register are unchanged by entering shutdown mode. however, all commands listed in table 16 are supported while in shutdown mode. execute command 15 (see ta ble 16 ) and set the lsb (d0) to 0 to exit shutdown mode. table 15 . truth table for shutdown mode linea r gain setting mode potentiometer mode a2 aw wb aw wb 0 n/a 1 open open r bs 1 open n/a 1 n/a 1 n/a 1 1 n/a = not applicable. ee prom or rdac register protection the eeprom and rdac registers can be protected by disabling any update to th e se registers . this can be done by using software or by using hardware. if the se registers are protect ed by software, set bit d0 and/or bit d1 ( see table 18 ) , which protect s the rdac and eeprom registers independently . if the register s are protected by hardware, pull the wp pin low. if the wp pin is pulled low when the part is executing a command, the protection is not enabled until the command is completed. when rdac is protected, the only operation allowed is to copy the eeprom into the rdac register . load rdac input regi ster ( lrdac ) lrdac software or hardware transfer s data from the input register to the rdac register (and therefore updates the wiper position ). b y default, the input register has the same value as the rdac register ; therefore, only the input register that has been updated using command 2 is updated. software lrdac , command 8, allows updating of a single rdac register or all of the channels at once (see ta ble 16 ). this is a synchronous update. the h ardware lrdac is completely asynchronous and cop ies the content of all the input register s into the associated rdac register s. if a command is executed , to avoid data corruption, a ny transition in the lrdac pin is ignored by the part. indep pin if the indep pin is pulled high at power - up, the part operates in linear gain setting mode, loading each string resistor, r aw and r wb , with the value stored into the eeprom (see table 17 ). if the pin is pulled low, the part powers up in potentiometer mode. the indep pin and the d2 bit are connected internally to a logic or gate, if any or both are 1 , the part can not operate in potentiometer mode ( see table 18). free datasheet http:///
data sheet AD5121/ad5141 rev. 0 | page 25 of 32 ta ble 16. advance command s operation truth table command number co ntrol bits [db15:db12] address bits [db11:db8] 1 data bits [db7:db0] 1 c3 c2 c1 c0 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 operation 0 0 0 0 0 x x x x x x x x x x x x nop: do nothing 1 0 0 0 1 0 a2 0 a0 d7 d6 d5 d4 d3 d2 d1 d0 write contents of serial register data to rdac 2 0 0 1 0 0 a2 0 a0 d7 d6 d5 d4 d3 d2 d1 d0 write contents of serial register data to input register 3 0 0 1 1 x a2 a1 a0 x x x x x x d1 d0 read back contents d1 d0 d ata 0 0 input register 0 1 eeprom 1 0 control register 1 1 rdac 4 0 1 0 0 a3 a2 0 a0 x x x x x x x 1 linear rdac increment 5 0 1 0 0 a3 a2 0 a0 x x x x x x x 0 linear rdac decrement 6 0 1 0 1 a3 a2 0 a0 x x x x x x x 1 +6 db rdac increment 7 0 1 0 1 a3 a2 0 a0 x x x x x x x 0 ? 6 db rdac decrement 8 0 1 1 0 a3 a2 0 a0 x x x x x x x x copy input register to rdac (software lrdac ) 9 0 1 1 1 0 a2 0 a0 x x x x x x x 1 copy rdac register to eeprom 10 0 1 1 1 0 a2 0 a0 x x x x x x x 0 copy eeprom into rdac 11 1 0 0 0 0 a2 0 a0 d7 d6 d5 d4 d3 d2 d1 d0 write contents of s erial register data to eeprom 12 1 0 0 1 a3 a2 0 a0 1 x x x x x x d0 top s cale d0 = 0; normal mode d0 = 1; shutdown mode 13 1 0 0 1 a3 a2 0 a0 0 x x x x x x d0 bottom s cale d0 = 1; e nter d0 = 0; e xit 14 1 0 1 1 x x x x x x x x x x x x software reset 15 1 1 0 0 a3 a2 0 a0 x x x x x x x d0 software shutdown d0 = 0; normal mode d0 = 1; device placed in shutdown mode 16 1 1 0 1 x x x x x x x x d3 d 2 d1 d0 copy serial register data to control register 1 x = dont care. table 17 . address bits a3 a2 a1 a0 potentiometer mode linear gain setting mode stored rdac memory input register rdac register input register rdac regi ster 1 x 1 x 1 x 1 all channels all channels all channels all channels not applicable 0 0 0 0 rdac rdac r wb r wb rdac/ r wb 0 1 0 0 not applicable not applicable r aw r aw not applicable 0 0 0 1 not applicable not applicable not applicable not applicable r aw 0 0 1 0 not applicable not applicable not applicable not applicable msb tolerance 0 0 1 1 not applicable not applicable not applicable not applicable lsb tolerance 1 x = dont care. free datasheet http:///
AD5121/ad5141 data sheet rev. 0 | pa ge 26 of 32 table 18. control register bit description s b it name description d0 rdac register write protect 0 = wiper position frozen to value in eeprom memory 1 = allow s update of wiper position through digital interface (default) d1 eeprom program enable 0 = eeprom program disabled 1 = enable s devi ce for eeprom program (default) d2 linea r setting mode / potentiometer mode 0 = potentiometer mode (default) 1 = linea r gain setting mode d3 burst m ode (i 2 c only) 0 = d isable d (default) 1 = enable d ( n o disable after stop or repeat start condition) free datasheet http:///
data sheet AD5121/ad5141 rev. 0 | page 27 of 32 rdac architecture to achieve optimum performance, analog devices, inc., has patented the rdac segmentation architecture for all the digital potentiometers. in particular, the AD5121 / ad5141 employ a t hree - stage segmentation approach , as shown in figure 41 . the AD5121 / ad5141 wiper switch is designed with the transmission gate cmos topology and with the gate voltage derived from v d d and v ss . 7-bit/8-bit address decoder r l w r l a r h r h r m r m b r m r m r h r h s ts s bs 10940-048 figure 41 . AD5121 / ad5141 sim plified rdac circuit top scale/bottom scale architecture in addition, the AD5121 / ad5141 include new position s to reduce the resistance between terminals. these position s are called bottom scale and top scale. at bottom scale, the typical wiper resistance decreases from 130 ? to 6 0 ? (r ab = 100 k ? ). at top scale, the resistance between terminal a and terminal w is decreased by 1 lsb , and the total resistance is reduced to 60 ? (r ab = 100 k ? ) . programming the vari able resistor rheostat operation 8% resistor tolerance the AD5121 / ad5141 operate in rheostat mode when only two te rminals are used as a variable resistor. the unused terminal can be floating , or it can be tied to terminal w , as shown in figure 42 . a w b a w b a w b 10940-049 figure 42 . rheostat mode configuration the nominal re sistance between terminal a and terminal b, r ab , is 10 k or 10 0 k , and has 128 /256 tap points accessed by the wiper terminal. the 7 - bit / 8 - bit data in the rdac latch is decoded to select one of the 128 /256 possible wiper settings . the general equations for determining the digitally programmed output r esistance between t erminal w and t erminal b are AD5121 : w ab wb r r d d r + = 128 ) ( from 0x00 to 0x7f ( 1 ) ad5141 : w ab wb r r d d r + = 256 ) ( from 0x00 to 0 x ff ( 2 ) where: d is the decimal equivalent of the binary code in the 7 - bit /8 - bit rdac register. r ab is the end - to - end resistance. r w is the wiper resistance . in potentiometer mode , s imilar to the mechanical potentiometer, the resistance of the rdac betwee n t erminal w and t erminal a also produces a digitally controlled complementary resistance, r wa . r wa also gives a maximum of 8% absolute resistance error. r wa starts at the maximum resistance value and decreases as the data loaded into the latch increases. the general equations for this operation are AD5121 : w ab aw r r d d r + ? = 128 128 ) ( from 0x00 to 0x7 f ( 3 ) ad5141 : w ab aw r r d d r + ? = 256 256 ) ( from 0x00 to 0xf f ( 4 ) where: d is the decimal equivalent of the binary code in the 7 - bit /8 - bit rdac register. r ab is the end - to - end resistance. r w is the wiper resistance . free datasheet http:///
AD5121/ad5141 data sheet rev. 0 | pa ge 28 of 32 if the part is configured in linear gain setting mode, the resistance between terminal w and terminal a is dire ctly proportional to the code loaded in the associate rdac register. the general equations for this operation are ad512 1 : w ab aw r r d d r + = 128 ) ( from 0x00 to 0x7f ( 5 ) ad5141 : w ab aw r r d d r + = 256 ) ( from 0x00 to 0xff ( 6 ) where: d is the decimal equivalent of the binary code in the 7 - bit /8 - bit rdac register. r ab is the end - to - end resistance. r w is the wiper resistance . in the bottom scale condition or top scale condition, a finite total wiper resistance of 40 is present. regardless of which setting the part is operating in, limit the current between terminal a to terminal b, terminal w to terminal a, and terminal w to terminal b, to the maximum continuous current of 6 ma or to the pulse current specified in table 7 . otherwise , degradation or possible destruction of the internal switch contact can occur. calculate the actual end - to - end resistance the resistance tolerance is stored in the internal memory during factory testing. therefore, t he actual end - to - end resistance can be calculated (which is valuable for calibration, tolerance matching , and precision applications). the resistance tolerance (in percentage) is stored in fixed point format, using a 16 - bit sign magn itude binary. the sign bit (0 = negative and 1 = positive) and the integer part are located in address 0x 0 2 , as shown in table 19. address 0x 0 3 contains the fractional part , as shown in ta ble 19. that is, if the data readback from address 0x 0 2 is 00000 010 , and the data readback from address 0x 0 3 is 10110000, the end - to - end resistance can be calculated a s follows. for memory map address 0x 0 2, db[7] = 0 = negative , and db[6:0] = 0000010 = 2 . for memory map address 0x 0 3, db[7:0] = 10110000 = 176 2 ? 8 = 0.6875 , and t herefore, tolerance = ?2.6875% , and r ab = 9.731 k?. programming the pote ntiometer divider voltage output operation the digital potentiometer easily generates a voltage divider a t wiper - to - b and wiper - to - a that is proportional to the input voltage at a to b, as shown in figure 43 . w a b v a v out v b 10940-050 figure 43 . potentiometer mode configuration connecting terminal a to 5 v and t erminal b to ground produces an output voltage at the wiper w to terminal b ranging from 0 v to 5 v. the general equation defining the output voltage at v w with respect to ground for any valid input voltage applied to terminal a and terminal b is b ab aw a ab wb w v r d r v r d r d v + = ) ( ) ( ) ( ( 7 ) w here: r wb ( d ) can be obtained from equation 1 and equation 2 . r aw ( d ) can be obtained from equation 3 and equation 4 . operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. unlike the rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors, r aw and r wb , and not the absolute values. therefore, the temperature drift reduces to 5 ppm/c. table 19 . end -to - end resistance tolerance bytes data byte memory map address db7 db6 db5 db4 db3 db2 db1 db0 0x02 sign 2 6 2 5 2 4 2 3 2 2 2 1 2 0 0x03 2 ? 1 2 ? 2 2 ? 3 2 ? 4 2 ? 5 2 ? 6 2 ? 7 2 ? 8 free datasheet http:///
data sheet AD5121/ad5141 rev. 0 | page 29 of 32 terminal voltage ope rating range the AD5121 / ad5141 are designed with internal esd diodes for protection. these diodes also set the voltage boundary of the terminal operating voltages. positive signals present on terminal a, terminal b, or terminal w that exceed v dd are clamped by the f orward - biased diode. there is no polarity constraint between v a , v w , and v b , but they cannot be higher than v dd or lower than v ss . v dd a w b v ss 10940-051 figure 44 . maximum terminal voltages set by v dd and v ss power - up sequence because there are diodes to limit the voltage compliance at terminal a, terminal b, and terminal w ( see figure 44 ), it is important to power up v dd first before applying any voltage to terminal a, terminal b, and terminal w. otherwise, th e diode is forward - biased such that v dd is powered unintentionally . the ideal power - up sequence is v ss , v dd , v logic , digital inputs, and v a , v b , and v w . the order of powering v a , v b , v w , and digital inputs is not important as long as they are powered after v ss , v dd , and v logic . regardless of the power - up sequence and the ramp rates of the power supplies, once v logic is powered, the power - on preset activates , which restores eeprom values to the rdac registers. layout and power sup ply biasing it is always a g ood practice to use a compact, minimum lead length layout design. ensure that t he leads to the input are as direct as possible with a minimum conductor length. ground paths should have low resistance and low inductance. it is also good practice to bypass t he power supplies with quality capacitors. apply l ow equivalent series resistance (esr) 1 f to 10 f tantalum or electrolytic capacitors at the supplies to minimize any transient disturbance and to filter low frequency ripple. figure 45 illustrates the basic supply bypassing configuration for the AD5121 / ad5141 . AD5121/ ad5141 10940-052 v d d v l ogi c v d d + v d d c 1 0 . 1 f c 3 10 f + c 2 0 . 1 f c 4 10 f v s s v l ogi c + c 5 0 . 1 f c 6 10 f g n d figure 45 . power supply bypassing free datasheet http:///
AD5121/ad5141 data sheet rev. 0 | pa ge 30 of 32 outline dimensions 3.10 3.00 sq 2.90 0.30 0.23 0.18 1.75 1.60 sq 1.45 08-16-2010-e 1 0.50 bsc bot t om view top view 16 5 8 9 12 13 4 exposed pa d pin 1 indic a t or 0.50 0.40 0.30 sea ting plane 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indic a t or for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.80 0.75 0.70 compliant to jedec standards mo-220-weed-6. figure 46 . 16 - lead lead frame chip scale package [lfcsp_ w q ] 3 mm 3 mm body, very very thin quad (cp - 16 - 22 ) dimensions shown in millimeters ordering guide model 1 , 2 r ab (k ) resolution interface temperat ure range package description package option branding ad512 1 bcpz10 - rl7 10 128 spi/i 2 c ? 40c to +125c 16- lead lfcsp_wq cp -16-22 dhe AD5121bcpz100 - rl7 100 128 spi/i 2 c ? 40c to +125c 16- lead lfcsp_wq cp -16-22 dhf ad514 1 bcpz10 - rl7 10 256 spi/i 2 c ? 40c to +125c 16- lead lfcsp_wq cp -16-22 dhc ad5141bcpz100 - rl7 100 256 spi/i 2 c ? 40c to +125c 16- lead lfcsp_wq cp -16-22 dhd eval - ad5141dbz evaluation board 1 z = rohs compliant part 2 the evaluation board is shipped with the 10 k? r ab resistor option; however, the board is compatible with both of the available resistor value options. free datasheet http:///
data sheet AD5121/ad5141 rev. 0 | page 31 of 32 notes free datasheet http:///
AD5121/ad5141 data sheet rev. 0 | pa ge 32 of 32 notes ? 2012 analog devices, inc. all r ights reserved. trademarks and registered trademarks are the property of their respective owners. d10940 - 0- 10/12(0) free datasheet http:///

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